1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel, which can reduce an address period and stabilizes discharge.
2. Description of the Background Art
In a plasma display panel (hereinafter, referred to as “PDP”), fluorescent materials are emitted by ultraviolet rays of 147 nm that are generated upon discharge of He+Xe or Ne+Xe gas to display an image including characters or graphics. Such a PDP can be easily made thin and large and can provide a high image quality with the recent development of the relevant technology. In particular, in a three-electrode AC surface discharge type PDP, a voltage required for discharge is lowered using wall charges accumulated on the surface upon discharge and electrodes are protected from sputtering occurring due to the discharge. It has advantages of low-voltage driving and long-life.
Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 30Y and a sustain electrode 30Z formed on an upper substrate 10, and an address electrode 20X formed on a lower substrate 18.
The scan electrode 30Y and the sustain electrode 30Z includes transparent electrodes 12Y and 12Z, and metal bus electrodes 13Y and 13Z, which have a line width smaller than that of the transparent electrodes 12Y and 12Z and are formed at one edges of the transparent electrodes, respectively. The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 using ITO (indium-tin-oxide).
The metal bus electrodes 13Y and 13Z are usually formed on the transparent electrodes 12Y and 12Z using chrome (Cr) and serve to reduce a drop in a voltage due to the transparent electrodes 12Y and 12Z having high resistance. An upper dielectric layer 14 and a protection film 16 are stacked on the upper substrate 10 on which the scan electrode 30Y and the sustain electrode 30Z are stacked.
Wall charges generated at the time of plasma discharge are accumulated on the upper dielectric layer 14. The protection film 16 serves to protect the upper dielectric layer 14 from the sputtering occurring during the plasma discharge and to increase discharge efficiency of a secondary cell. The protection film 16 is usually formed using magnesium oxide (MgO).
The address electrode 20X is formed in a direction that intersects the scan electrode 30Y and sustain electrode 30Z. A lower dielectric layer 22 and a diaphragm 24 are formed on the lower substrate 18 in which the address electrode 20X is formed. A fluorescent layer 26 is formed on the surface of the lower dielectric layer 22 and diaphragms 24. The diaphragms 24 are formed in parallel to the address electrode 20X to physically divide the discharge cell, and serve to prevent ultraviolet rays and a visible ray generated due to the discharge from leaking toward neighboring discharge cells. The fluorescent layer 26 is excited by ultraviolet rays generated during the plasma discharge to generate a visible ray of one of red, green and blue. An inert mixed gas such as He+Xe or Ne+Xe for discharge is inserted into the discharge space of the discharge cell provided between the upper and lower substrates 10 and 18 and the diaphragms 24.
Such a three-electrode AC surface discharge type PDP is driven in such a way that one frame is divided into several sub fields of different emission numbers in order to implement the gray level of an image. Each sub field is divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing the gray level according to the number of discharge. If an image is to be represented using 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into 8 sub fields SF1 to SF8, as shown in FIG. 2.
Each of the 8 sub fields SF1 to SF8 is divided into the reset period, the address period and the sustain period. The reset period and the address period of each sub field are the same every sub field, whereas the sustain period and its discharge number increase in the ratio of 2n (n=0,1,2,3,4,5,6,7) in each sub field. Since the sustain periods becomes different in respective sub fields as such, the gray level of the image can be implemented.
The driving method of such a PDP is mainly classified into a selective writing mode and a selective erasing mode according to whether the discharge cell selected by address discharge is emitted.
In the selective writing mode, all of cells are turned off during the reset period and on-cells to be turned on are selected during the address period. Further, in the selective writing mode, discharge of the on-cells selected by address discharge is maintained during the sustain period, so that an image is displayed.
In the selective erasing mode, all of cells are turned on during the reset period and off-cells to be turned off are selected during the address period. Moreover, in the selective erasing mode, discharge of on-cells except for the off-cells selected by address discharge are kept during the sustain period, so that an image is displayed.
The selective writing mode has an advantage that it has a gray representation level wider than that of the selective erasing mode, but has a disadvantage that its address period is longer than that of the selective erasing mode. On the contrary, the selective erasing mode is advantageous in high-speed driving but is disadvantageous in the contrast property compared to the selective writing mode since all the cells are turned on during the reset period being a non-display period.
A so-called “SWSE mode having better advantages than the selective writing mode and the selective erasing mode was proposed in Korean Patent Application Nos. 10-2000-0012669, 10-2000-0053214, 10-2001-0003003, 10-2001-0006492, 10-2002-0082512, 10-2002-0082513, 10-2002-0082576 and so one, all of which were applied by the present applicant. An example of a driving signal of the SWSE mode is shown in FIG. 3.
Referring to FIG. 3, in the SWSE mode, the PDP is driven with one frame period time-divided into a plurality of selective writing sub fields SW and a plurality of selective erasing sub fields SE.
During the reset period of the selective writing sub fields SW, a ramp waveform (Ruy) of rising inclination where a voltage increases up to a setup voltage (Vsetup) is applied to all scan electrodes Y. At the same time, 0V or the ground voltage GND is applied to the sustain electrodes Z and the address electrodes X. Writing dark discharge occurs within cells of the entire screen between the scan electrodes Y and the address electrodes X and between the scan electrodes Y and the sustain electrodes Z by means of the rising ramp waveform (Ruy).
Wall charges of the positive polarity (+) are accumulated on the address electrodes X and the sustain electrodes Z and wall charges of the negative polarity (−) are accumulated on the scan electrodes Y, by means of the writing dark discharge. After the writing dark discharge, a ramp waveform (Rdy) of falling inclination where a voltage decreases from the sustain voltage (Vs) to the negative polarity voltage is applied to the scan electrodes Y. At the same time, a DC bias voltage (DCz) of the sustain voltage (Vs) is applied to the sustain electrodes Z.
Erasing dark discharge occurs between the scan electrodes Y and the sustain electrodes Z and between the scan electrodes Y and the address electrodes X because of a voltage difference between the falling ramp waveform (Rdy) and the DC bias voltage (DCz). The erasing dark discharge serves to erase excessive wall charges that do not contribute to the address discharge among the wall charges generated by the rising ramp waveform (Rdy), so that the wall charges uniformly remain within the cells of the entire screen.
During the address period of the selective writing sub fields SW, a writing scan pulse (scw) is sequentially applied to the scan electrodes Y and a writing data pulse (dw) synchronized to the writing scan pulse (scw) is applied to the address electrodes X. Further, a DC bias voltage (DCz) is continuously applied to the sustain electrodes Z.
As the voltage difference between the writing scan pulse (scw) and the writing data pulse (dw) and the wall voltage initialized during the reset period are added, writing discharge occurs within the on-cells to which the writing data pulse (dw) is applied. While wall charges of the positive polarity are being accumulated on the scan electrodes Y by means of the writing discharge, the polarity of the wall charges is reversed to the positive polarity and wall charges of the negative polarity are accumulated on the sustain electrodes Z and the address electrodes X.
During the sustain period of the selective writing sub fields SW, a sustain pulse (sus) of a sustain voltage (Vs) is alternately applied to the scan electrodes Y and the sustain electrodes Z. Whenever the sustain pulse (sus) is supplied as such, sustain discharge is generated in the on-cells during the writing address period.
After the last sustain discharge is generated, an erasing ramp waveform(ers) that gradually rises up to the sustain voltage (Vs) is applied. The wall charges generated by the sustain discharge are erased, while the erasing discharge occurs within the on-cells, by means of the erasing ramp waveform(ers).
During the address period of the selective erasing sub fields SE, an erasing scan pulse (sce) is sequentially applied to the scan electrodes Y, and an erasing data pulse (de) synchronized to the erasing scan pulse (sce) is applied to the address electrodes X. During the address period, 0V or a ground voltage GND is applied to the sustain electrodes Z. As a voltage difference between the scan pulse (sce) and the erasing data (de) and the wall voltage within the cells are added, erasing discharge is generated within the off-cells to which the erasing data pulse SED is applied. By means of the erasing discharge, the wall charges within the off-cells are erased to the extent that discharge does not occur although the sustain voltage is applied thereto.
During the sustain period of the selective erasing sub fields SE, the sustain pulse (sus) of the sustain voltage (Vs) is alternately applied to the scan electrodes Y and the sustain electrodes Z. Whenever the sustain pulse (sus) is applied, sustain discharge occurs in the on-cells that are not selected during the erasing address period.
The biggest difference between the selective writing sub fields SW of the SWSE mode and the selective erasing sub fields SE is the address discharge properties. In the selective writing sub fields SW, strong reversion is necessary since the wall charge polarity on the scan electrodes Y and the sustain electrodes Z has to be inversed or reversed by means of address discharge within the on-cells that generate sustain discharge.
For this reason, since an address discharge time necessary to generate the writing address discharge is relatively long, the address period becomes long. On the contrary, in the selective erasing sub fields SE, the wall charge polarity on the scan electrodes Y and the sustain electrodes Z is not inversed but the amount of the wall charges is reduced. Due to this, since the address discharge time for generating the erasing address discharge becomes short compared to the writing address discharge, the address period can be relatively shortened.
The driving method of the PDP, however, has problems that the address period is long and discharge is unstable in a low gray level because of delayed address discharge. If the address period becomes long, the sustain period is relatively shortened during a limited frame period, thus making luminance degrade. As a result, it is difficult to add more sub fields during one frame period in order to reduce factors of lowering in image quality such as motion picture quasi-contour noise.
Discharge instability in the low gray level will now be described in detail. Generally, the number of the sustain pulse and the number of discharge are not coincident each other. Discharge is unstable when the sustain pulse is generated initially. After that, when the sustain pulse is generated, luminance increases while discharge is gradually stabilized. In other words, when the sustain pulse is generated initially, discharge may not happen. Accordingly, as the number of consecutive sustain pulse is small in the low gray level, discharge is difficult to occur in a stable state.